PLL Frequency Synthesizers Based on the DDS in Feedback Loop

Andrew Polyakov, Peter Bobkovich, Andrew Kuzmenkov

EDICON 2013, Beijing China, 7 pp.

Abstract

This paper discusses the benefits and disadvantages of the one-loop PLL architecture based on the DDS in feedback loop. It presents mathematical model of phase noise sources with equations for its estimation while taking into account the performance of present-day components. The paper also presents spur-reducing approach based on the variable reference frequency. The equations for evaluating “bad” frequencies and spur offsets are given. As a measure of spur the empirical cumulative distribution of SFDR normalized to 1 GHz is used. It allows to evaluate and compare the quality of different synthesizers regardless of their frequency range. Synthesizers with single and dual frequency reference were compared using this measure. The paper also considers the locking process of the PLL based on the DDS in the loop.

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Keywords: PLL; DDS; phase noise; spur; SFDR.